1. Field of the Invention
The present invention relates to a NAND nonvolatile semiconductor memory device that has a memory cell array region and a selection gate region, and a method of manufacturing a NAND nonvolatile semiconductor memory device.
2. Background Art
In recent years, the microfabrication technique for semiconductor devices has advanced, and a minimum feature size of 50 nm or smaller has been achieved.
As for a NAND nonvolatile semiconductor memory device (NAND flash memory), interference between adjacent memories due to the coupling capacitance thereof becomes more significant as the miniaturization proceeds. In addition, the difficulty of machining significantly increases as the miniaturization proceeds, so that reducing the vertical size of the NAND flash memory (reducing the thickness of the film structure) has become an important issue.
Many conventional flash memories in practical use have a memory cell structure including a floating gate. In the case where the selection gate is formed at the same time as the control gate, the interpoly insulating film is partially removed to make the control gate and the floating gate electrically continuous (see Japanese Patent Laid-Open Publication No. 2002-176114, for example).
To achieve desired characteristics, the thickness of the device isolation insulating film between the Poly-Si layer serving as the control gate and the channel region (silicon substrate surface) has to be sufficiently greater than the thickness of the gate insulating film.
However, due to fluctuation in the process of partially removing the interpoly insulating film described above, the device isolation insulating film can be excessively etched. In that case, the Poly-Si layer serving as the control gate and the channel region are excessively close to each other. As a result, a problem can arise that the yield decreases because the withstand voltage of the selection gate decreases, the leak current increases, or the operating threshold voltage varies, for example.